The present invention relates to a semiconductor integrated circuit device including memory cells, each cell having a pair of complementary insulated gate field effect transistors, and to a method for producing the device. More particularly, it relates to a semiconductor integrated circuit memory device with extremely small-sized memory cells, arranged in a high density.
U.S. Pat. No. 3,919,569 discloses a two-device, semiconductor memory cell constructed of a pair of complementary insulated gate field effect transistors (hereinafter abbreviated "IGFET's"). These transistors mutually share an impurity region that works as a source or a drain region of a first IGFET and also as a channel region of a second IGFET. In this two-device memory cell, P-type source and drain regions are formed in an N-type semiconductor substrate, in order to form a first IGFET. An N-type region is formed within one of the source and drain regions, which becomes a substrate region of a second IGFET. A continuous gate electrode is provided via a gate insulating film over the semiconductor substrate, between the source and drain regions of the first IGFET. The gate extends over either the source or drain, as the substrate region of the second IGFET, which uses the semiconductor substrate and the N-type region as a source and a drain, respectively. In this memory cell, the electric charges, which are stored in the substrate region of the second IGFET, are controlled by the first IGFET, in order to vary a threshold voltage of the second IGFET. Depending upon its threshold voltage, the second IGFET becomes either conductive or non-conductive in response to a constant voltage applied to its gate electrode.
The principal features of this prior art memory cell are that the memory cell, per se, can be a small size and that two kinds of currents having different magnitudes can be made to store information. The latter feature makes it possible to achieve a read-out of the memory by sensing a d.c. current. As a result, an output voltage applied to a sense amplifier can be made large enough, as long as a sufficient time is spent for the read-out. Hence, a sensitivity of the sense amplifier does not impose a limitation upon a high density integration of the memory circuit using this memory cell. Accordingly, this memory cell is well adapted for use in a high density formation and a large capacity formation of a semiconductor integrated circuit memory.
The semiconductor integrated circuit memory is packaged by a use of plastics or ceramics packaging materials. These packaging materials contain minute amounts of uranium, thorium, etc. Alpha particles generated from uranium, thorium, etc. travel straight through silicon, by about 25 .mu.m. During that travel, about two million pairs of electrons and holes are produced. The depletion layer formed between one of the P-type source and drain regions is maintained in an electrically floating condition. The N-type region is formed in this depletion layer, and in the surrounding N-type semiconductor substrate. Accordingly, the produced pairs of electrons and holes move according to the electric field in the back-biased depletion layer. Holes move to the P-type region, while electrons move to the surrounding N-type semiconductor substrate, and afterward, all the electric charges stored in the floating P-type region (the substrate region of the second IGFET) are reduced.
Some other alpha particles penetrate through the depletion layer and come to the N-type semiconductor substrate, where the pairs of electrons and holes are produced and diffused as separated individually. These electrons and holes have a long life because a density of recombination centers is low there. Several tens of percents of the holes produced in the N-type semiconductor substrate may reach the above-mentioned depletion layer and then reach the floating P-type region, owing to an electric field applied across the depletion layer. Therefore, the amount of electric charges stored in the floating P-type region are further reduced. Such undesired effects by alpha particles should be eliminated.
The prior art two-device memory cell has another disadvantage in that the plan configuration of the memory cell, per se, is large, because one of the P-type source and drain regions of a first IGFET should be so large that the N-type region formed therewith can be isolated from the N-type semiconductor substrate. It may also be possible to reduce the memory cell size by bringing the sides of the larger one of the P-type source and drain regions and the N-type region therein into contact with a field insulating film buried in the substrate. With such a configuration, the larger P-type region extends under the field insulating film. Therefore, the field insulating film should be formed with a sufficient width in order that the adjacent memory cells may not influence each other. Accordingly, an overall size of the memory cell cannot be made very small.